A Simple Method for Detecting Periodic Signals in Sparse Astronomical Event Data

We present a simple method to detect periodic signals in sparse astronomical event data. The method is particularly appropriate for gamma-ray astronomy where the number of available photons is sparse in time and Poissonian noise dominates the statistics. It is based on an autocorrelation function, which provides phase independence. We have implemented and successfully applied this method on simulated data. This paper presents some numerical results and a description of the model used to generate the synthetic data along with a formal definition of the signal-to-noise ratio in the generated time series

Design architectures of the CMOS power amplifier for 2.4 GHz ISM band applications: An overview

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications

Multichannel Time Synchronization Based on PTP through a High Voltage Isolation Buffer Network Interface for Thick-GEM Detectors

Data logging and complex algorithm implementations acting on multichannel systems with independent devices require the use of time synchronization. In the case of Gas Electron Multipliers (GEM) and Thick-GEM (THGEM) detectors, the biasing potential can be generated at the detector level via DC to DC converters operating at floating voltage. In this case, high voltage isolation buffers may be used to allow communication between the different channels. However, their use add non-negligible delays in the transmission channel, complicating the synchronization. Implementation of a simplified precise time protocol is presented for handling the synchronization on the Field Programmable Gate Array (FPGA) side of a Xilinx SoC Zynq ZC7Z030. The synchronization is done through a high voltage isolated bidirectional network interface built on a custom board attached to a commercial CIAA_ACC carrier. The results of the synchronization are shown through oscilloscope captures measuring the time drift over long periods of time, achieving synchronization in the order of nanoseconds

High Performance 128-Channel Acquisition System for Electrophysiological Signals

The increased popularity of investigations and exploits in the fields of neurological rehabilitation, human emotion recognition, and other relevant brain-computer interfaces demand the need for flexible electrophysiology data acquisition systems. Such systems often require to be multi-modal and multi-channel capable of acquiring and processing several different types of physiological signals simultaneously in realtime. Developments of modular and scalable electrophysiological data acquisition systems for experimental research enhance understanding and progress in the field. To contribute to such an endeavor, we present an open-source hardware project called High-Channel Count Electrophysiology or HiCCE, targeting to produce an easily-adaptable, cost-effective, and affordable electrophysiological acquisition system as an alternative solution for mostly available commercial tools and the current state of the art in the field. In this paper, we describe the design and validation of the entire chain of the HiCCE-128 electrophysiological data acquisition system. The system comprises of 128 independent channels capable of acquiring signal at 31.25 kHz, with 16 effective bits per channel with a measured noise level of about 3 μV. The reliability and feasibility of the implemented system have been confirmed through a series of tests and real-world applications. The modular design methodology based on the FPGA Mezzanine Card (FMC) standard allows the connection of the HiCCE-128 board to programmable system-on-chip carrier devices through the high-speed FMC link. The implemented architecture enables end users to add various high-response electrophysiological signal processing techniques in the field programmable gate arrays (FPGA) part of the system on chip (SoC) device on each channel in parallel according to application specification

Collins and Sivers asymmetries in muonproduction of pions and kaons off transversely polarised protons

Measurements of the Collins and Sivers asymmetries for charged pions and charged and neutral kaons produced in semi-inclusive deep-inelastic scattering of high energy muons off transversely polarised protons are presented. The results were obtained using all the available COMPASS proton data, which were taken in the years 2007 and 2010. The Collins asymmetries exhibit in the valence region a non-zero signal for pions and there are hints of non-zero signal also for kaons. The Sivers asymmetries are found to be positive for positive pions and kaons and compatible with zero otherwise. © 2015

Building an Evolvable Low-Cost HW/SW Educational Platform--Application to Virtual Instrumentation

This paper describes a hardware/software FPGA-based platform. Its goal is to provide a reusable low-cost system for teaching system-level design, with an emphasis on design reuse as an effective mean to cope with an ever growing design complexity. An open source strategy promotes cross-university collaboration by relying on previously developed software. The first implementation examples target the area of Reconfigurable Virtual Instrumentation (RVI), which in turn provides a low-cost solution for teaching electronic instrumentation

Corrections to “A Survey on FPGA-Based Heterogeneous Clusters Architectures”

In the above article [1], two references were missing [2], [3]

HyperFPGA: A possible general purpose reconfigurable hardware for custom supercomputing

International audience— In this work we propose and analyze a possible hardware architecture for experimentation on fine-grained reconfigurable supercomputing based on modern Field Programmable Gate Array (FPGA) technology. It is proposed a scalable cubic array of elementary computational units which are interconnected according to a tridimensional toroidal mesh network. Each computational unit is essentially formed by an FPGA plus an onboard external RAM memory. While the adjacent units in the bulk are directly interconnected through the regular FPGA IOs; the external units at opposite faces of the cubic array are interconnected by mean of high speed serial links in order to grant homogeneous data transfer bandwidth among all topologically adjacent units. Among several relevant issues we discuss the feasibility, scalability and portability